Now we all say that Moore’s Law is gradually reaching its limit. As an economic law, Moore’s Law gradually does not have cost-economic benefits. First of all, high-end process nodes have reached the limit of physical transistor size, and as server CPU and GPU die sizes continue to increase over time, the die size continues to grow and is approaching the limit. Therefore, the industry began to consider starting from different dimensions to continue Moore’s Law.
IC design development shifts to 3D dimension
The composition of a chip is mainly divided into four levels: the bottom device, the standard cell library, the on-chip memory SRAM, a block of the chip will be made on the SRAM, and then the system is on top. In order to keep Moore’s Law going down, one of the technical efforts is More Moore. The exploration in this area is mainly aluminum dielectric, then copper, then High-K, FinFET, and GAA after 3 nanometers, relying on these Technology Moore’s Law continues to advance in advanced technology.
But relying on this dimension alone is not enough to support Moore’s Law going down, because the cost does not see a significant reduction. Therefore, the industry is still exploring another dimension, which is More than Moore. From a system perspective, work hard on packaging and take the stacking route, such as the current 2.5D packaging and 3D packaging.
The picture below is a package diagram obtained under a microscope. There will be a large solder ball inside the package. The size of the solder ball affects the bandwidth and speed of the chip. It can be seen that once the dimensions of 2D to 3D are changed, the obvious benefit is that the connection of the solder ball becomes shorter. After the connection becomes shorter, the power consumption will be lower. After the delay on the line is reduced, the chip will become Will run faster than before and get better performance. The more obvious benefit is that because the chips are stacked, the size of the package will be much smaller. The last is a better yield. You must know that during the tape-out process, the yield and area have an exponential relationship. The larger the area, the lower the yield.
However, 3D-IC design currently faces many challenges. The first is the challenge of aggregation and management, including die placement and Bump planning, and the SoC and packaging teams are fighting on their own, lacking a unified database representing multiple technologies; and another. The challenge is system-level verification, which requires cross-chip/Chiplet and package thermal analysis, and system-level connection verification between dies. The 3D STA sign-off corner will also have an “explosive” increase. The current solution status of the EDA industry is disjointed, one-sided, point-of-tool, unable to explore/lack of early feedback, resulting in over-design of a single die in the stack, which is costly. All of this makes 3D STA much more complex than 2D.
In response to these industry pain points and the development trend of advanced packaging technology, Cadence released a breakthrough new product.
Integrity? 3D-IC platform: Driven by the system Chiplet PPA
It should be noted that in the field of advanced packaging, not only packaging plants and fabs are working hard, EDA software vendors are also heavy explorers of advanced packaging. For example, Cadence has worked in the field of Multi-Chiplet packaging for more than 20 years. From 1980 to system-level packaging, to RF modules in 2004, 2.5D technology in 2010, and in 2012 Started to do embedded bridging. Up to now, in the more popular FOWLP, Bumpless 3D integration and Co-package, etc., Cadence is constantly working on the direction. Among them, Co-package refers to not only silicon chips, but Cadence can even Stacked with silicon.
According to Liu Miao, Senior Group Director of Product Engineering of the Cadence Digital and Sign-off Division, Cadence has been working hard to transform these years. In the past, we only made EDA tools. Later, we made more system-level innovations. Finally, we hope to achieve universality. 3D-IC is a system innovation that can help customers solve current pain points and development trends in the next ten years.
Liu Miao, Senior Group Director of Product Engineering, Cadence Digital and Sign-off Division
Liu Miao further pointed out that Cadence 3D-IC will start from these dimensions in the next ten years. The first is the key technology of advanced packaging. There are two trends in the packaging field, namely analog and digitalization and packaging wafering. Cadence will embrace These changes have made great efforts to advanced packaging. Then there is digital design and sign-off. We propose system-level PPA, which must be compatible with digital design, so we must have a unified platform. To do 3D stacking, only digital does not appear to be so comprehensive, so analog design and verification must be added. Finally, thermal simulation and signal integrity analysis must be done. All of this is placed in this Integrity 3D-IC platform.
Integrity? 3D-IC platform is the industry’s first complete high-capacity 3D-IC platform, which integrates design planning, physical implementation and system analysis into a single management interface. The Integrity 3D-IC platform supports Cadence’s third-generation 3D-IC solution. Customers can use the integrated thermal, power and static timing analysis functions of the platform to optimize the power consumption, performance and area of the chip (Chilet) driven by the system Target (PPA).
So what are the “magic weapons” of Integrity? 3D-IC platform? Let us talk about it.
Everything is active. Cadence understands that the source is to have a unified platform. Cadence’s Integrity platform is compatible with data and simulation. It can achieve a multi-level, multi-technology, multi-level, multi-model on-demand database. It is not easy to achieve this. It took many years for Cadence to make this compatibility. In fact, in order to make digital and analog compatible, Cadence launched an open database as early as 20 years ago, and now it is one step closer. With a unified management interface and database, SoC and packaging design teams can perform fully synchronized collaborative optimization of the complete system, and integrate system-level feedback more efficiently.
Earlier we mentioned some challenges related to 3D IC design. Compared with 2D design, 3D design has a longer cycle. In response to this problem, Cadence can avoid heat dissipation and power consumption in the early stage through early electric heating and cross-chip STA. , In order to create a robust 3D-IC design, using early system-level feedback to optimize the system-wide PPA.
Another is the Signoff of timing. 3D timing analysis is much more complicated than 2D. In this regard, Cadence has fast and automatic inter-die analysis technology (RAID), which can significantly reduce STA Corner data and turnaround cycles. At the same time, Cadence also introduced another parallel multi-mode multi-corner (C-MMMC) technology, which can simplify project management and machine resources. Both of these technologies are Cadence’s strengths. Die-level layering can also significantly reduce the amount of data in the boundary model. Finally, there is the Tempus ECO option. Through the parallel multi-die 3D-IC timing ECO, the system driving PPA can be optimized.
The following figure shows the process given to the customer. Integrity 3D-IC is a complete and modular platform that can be used for Native 3D Partitioning. At the beginning, the system-level engineer decides which is on the top and which is on the bottom. After finishing it, you can do the partition. Do System-Level Planning in the system level. After finishing, you can make die’s floorplan and so on. Eventually realize the PPA goal driven by the system.
Facilitate the development of China’s 3D stacking technology
Integrity 3D-IC received early response from customers when it was released. imec also said that thanks to the long-term cooperation with Cadence, we have successfully found an automated method for designing partitions to create the best 3D stack, further improving the performance of advanced process node designs by increasing the available memory bandwidth, and reducing power consumption. According to the results of our research team’s multi-core high-performance design, the Cadence Integrity 3D-IC platform integrates the memory in the logic flow, achieving cross-die (cross-die) design planning, design implementation, and multi-Die STA.
In the previous article, we mentioned that Cadence can package light and silicon together. In this regard, Cadence and Lightelligence have related cooperation. Lightelligence has been using multi-chip stacking technology over the years, with the intention of using optical computing technology to accelerate the evolution of AI. The Integrity 3D-IC platform can help Lightelligence use optical computing technology to accelerate AI design and achieve next-generation innovation.
“China is still leading in the field of 3D,” Liu Miao admitted frankly. In addition to Lightelligence, ZTE Microelectronics is also a partner of Cadence. ZTE attaches great importance to 3D stacking, especially communication 3D stacking. The power consumption of communication is a major issue to be solved. problem. The Integrity 3D-IC platform perfectly integrates optimized mid-level design implementation and system analysis to provide fast and complete system analysis, enabling ZTE Microelectronics to provide designs that meet the memory bandwidth requirements of ultra-large-scale computing and 5G communication applications.
The release of the Integrity 3D-IC platform will be of great benefit to the domestic multi-chip 3D stacking technology. It supports a wide range of application scenarios such as ultra-large-scale computing, consumer electronics, 5G communications, mobile and automobiles. Compared with the traditional single disjointed Die-by-Die design implementation method, chip design engineers can use the Integrity 3D-IC platform to obtain higher production efficiency.
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