“The DSP and the single-chip microcomputer constitute a dual-CPU processor platform, which can make full use of the processing capability of the DSP for large-capacity data and complex algorithms, as well as the control capability of the single-chip microcomputer interface. The fast and correct communication between the DSP and the single-chip computer is the key issue of constructing a dual-CPU processor. In the following, three connection methods of serial SCI, SPI and parallel HPI are designed respectively on this issue.

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Authors: Liu Zheng, Ye Hanmin

The DSP and the single-chip microcomputer constitute a dual-CPU processor platform, which can make full use of the processing capability of the DSP for large-capacity data and complex algorithms, as well as the control capability of the single-chip microcomputer interface. The fast and correct communication between the DSP and the single-chip computer is the key issue of constructing a dual-CPU processor. In the following, three connection methods of serial SCI, SPI and parallel HPI are designed respectively on this issue.

1 Serial communication design and implementation

1 1 SCI serial communication design

1.1.1 The principle of multi-channel buffer serial port MCBSP

TMS320VC5402 (VC5402 for short) provides two multi-channel buffered serial ports McBSP that support high-speed, full-duplex, buffered, and multiple data formats. MCESP is divided into data path and control path. ① The data path is responsible for completing the sending and receiving of data. The CPU or DMAC can write data to the data transmission register DXR, and the data in DXR is output to the DX pin through the transmission shift register XSR. The DR pin receives data to the receive shift register RSR, then copies it to the receive buffer register RBR, and finally copies it to the data receive register DRR. These two data multi-level buffering methods enable data movement and off-chip data communication to be performed simultaneously. ②The control path is responsible for the generation of internal clock, frame synchronization signal generation, signal control and multi-channel selection. in addition. It also has the function of sending interrupt signals to the CPU and sending synchronization events to the DMAC. The MCBSP clock and frame synchronization signal are controlled by the CLKR, CLKX, FXR, FSX pins. The receiver and transmitter can choose the external clock and frame synchronization signal independently of each other, or they can choose to generate the clock and frame synchronization by the internal sample rate generator. Signal. A frame sync pulse is active to indicate the start of a transmission.

1.1.2 SCI serial interface design

Set the McRSP output clock and frame synchronization signal of VC5402 to be generated by the internal sampling rate generator. The internal data clock CLKG and frame synchronization signal FSG drive the transmit clock CLKX and frame synchronization FSX (CLKXM=l, FSXM=l, FSGM=1), input The clock is also generated by the internal sample rate generator. The internal data clock CLKG drives the receive clock CLKR (CLKRM=1), while the CPU clock drives the sample rate generator (CLKSM=1). Considering that the first bit in the data frame sent by the serial port of AT89C51 (C51 for short) is the start bit, this bit can be used to drive the input frame synchronization signal FSR, and at the same time, set the ignore frame synchronization signal flag to 1. Among them, FSG frame sync pulse width=(FWID+1)・CLKG; FSG frame sync pulse period=(FPER+1)・CLKG; sampling rate generator frequency division factor (sampling rate=baud rate)=FIN/(CLKGDV+ 1).

The SCI serial port connection is shown in Figure 1.

1.1.3 Handling of inconsistent baud rates

VC5402 initialization (take Figure 1 as an example):

STM#SRGR1, SPSA1
STM#ooFEH, SPSD1; FSG frame synchronization pulse width bit is 1 CLKG;
The baud rate is 100 MHz/(0X(OFF)=392 156 b/s
STM#SRGR2, SPSA1
STM#3D00H, SPSDl; the internal sample rate generator clock is driven by the CPU
C51 initialization:
MOV TMOD, #20H
MOVTL1, #FFH
MOVTHl, #FFH; C51 baud rate=(2SMOD/32)*(fosc/12)[1/(256-initial value)]-24 509 b/s
MOV SCON, #50H; set serial port mode l, 10-bit data per frame.Allow to receive
MOV PCON, #80H; set SMOD=1
VC5402 baud rate / C51 baud rate = (392 156 / 24 509) = 16.000 49

When VC5402 sends 16 bits of data, C51 only samples 1 bit of data. Open up a space in the VC5402 memory to expand the 8-bit data sent each time, 1-bit is expanded to 16-bit, 0 is 0000H, l is FFFFH, and a total of 128 bits are expanded. The 16-bit start bit 0000H is added to the head of the data, and the stop bit FFFFH is added to the tail of the data. Set XWDLEN=000 (1 word contains 8 bits) in the VC5402 sending control register XCR, then the 8-bit data to be sent can be encapsulated into 1 frame of 10-word data. This also conforms to the data format of 1 frame of 10 bits in C51 serial port 1 mode. C51 receives data at the VC5402 sampling rate of 1/16, 0000H is sampled as 0, and FFFFH is sampled as 1, so that the received 200 bits can be restored to 8-bit data, and the stop bit enters RB8.

Every time C51 sends 1 bit of data, VC5402 needs to sample 16-bit data. The start bit of the 10-bit data sent by C51 at a time triggers the synchronization of the received frame of VC5402. Because VC5402 receives data with 16 times the sampling rate of C51, 1-bit sampling is 16 bits, 0 sampling is 0000H, and 1 sampling is FFFFH. Only the first 9 bits of the 10 bits sent are sampled, and the 9 bits are packed into 144 bits, that is, the received 1 frame of data is completed. VC5402 stores the received 144-bit data in the opened memory space, discards the first 16 bits, and divides the remaining 128 bits into 8 groups of 16 bits each. Comparing the 8 bits in the middle, if more than 4 bits are 1, the 16 bits are 1, otherwise, it is 0. This restores the received 144 bits to 8-bit data.

In order to prevent the CPU from being interrupted frequently by data reception and transmission, DMA and MCBSP are used jointly to control the reception and transmission of data. RRDY directly drives MCBSP to receive data events (REVENT events) from DMAC, and XRDY directly drives MCBSP to send data events (XEVENT events) to DMAC.

The SCI communication protocol is shown in Figure 2

1.2 SPI serial communication design

Set C51 as the master and VC5402 as the slave. The clock stop mode of McBSP (CLKSTP=1X) is compatible with SPI mode, and the receive part and the transmit part are internally synchronized. McBSP can act as SPI slave or master. The sending clock BCLKX is used as the shift clock SCK of the SPI protocol, the sending frame synchronization signal BFSX is used as the slave enable signal nSS, and the receiving clock BCLKR and the receiving frame synchronization signal BFSR are not used. They are directly connected internally to BCLKX and BFSX respectively. BDX as MISO, and BDR as MOSI, transmit and receive with the same word length.

Parallel ports P1.1 and P1.2 in C51 are connected with VC5402 as extended serial SPI input and output ports, P1.0 is used as serial clock output port, and P1.3 is used as frame synchronization signal output port.

The SPI serial port connection is shown in Figure 3.

VC5402 initialization program (take Figure 3 as an example):
STM#SPCRll, SPSA1; set the clock stop bit to enter the SPI mode of MCBSP
STM#0X1000, SPSDl; clock starts on rising edge (no delay)
STM#SPCRl2, SPSA1
STM#0X0040, SPSDl; XINT is driven by XRDY (ie suffix)
STM#PCR1, SPSA1
STM#0X000C, SPSDl; set the sending and receiving clock and synchronization frame
STM#RCRll. SPSAl
STM#0X0000, SPSD1; receive data 1 frame 1 word. 1 word 8 bits
STM#XCRll, SPSA1
STM#0X0000, SPSD1;; Send data 1 frame and 1 word. 1 word 8 bits;

The shift clock that P1.0 sends to VC5402 is the clock that guarantees the DSP to correctly sample the received and sent data. It should be guaranteed to be consistent with the clock of C51’s sampling to receive and transmit data. In order to make the master-slave synchronization.

2 Parallel Communication Design and Implementation

2.1 Principle of HPI interface of VC5402

HPI-8 is an 8-bit (HD0-HD7) parallel interface connecting DSP and host device or host processor. The DSP and the host exchange data through the on-chip RAM of the DSP, and the entire on-chip RAM can be used as the memory of HPI-8. The HPIA address register can only be directly accessed by the host, and stores the address of the currently addressed memory; the HPID data latch can only be directly accessed by the host, and stores the current data to be written or read; the HPIC control register can be accessed by the host and the VC5402 common access. The hardware interrupt logic of HPI itself can complete the handshake between the master and slave devices. The host generates a DSP interrupt by setting a specific bit in the HPIC, and the DSP interrupts the host through the nHINT pin. The HRDY pin is used to automatically adjust the speed at which the host accesses the HPI, so that the slow external host can be well matched to the DSP. HRDY is enabled by HCS, that is, HRDY is always high when HCS is high, and when EMUl/nOFF is low, HDRY outputs high resistance.

The HPI connection is shown in Figure 4.

2.2 Parallel Interface Design

Set C51 as the master and VC5402 as the slave. The PO port of C51 is connected with the 8-bit data lines HD0-HD7 of HPI as a data transmission channel, and P1.0-P1.3 are set to output and control the operation of the HPI port. Among them, P1.0 is connected to HR/W as a read-write control strobe signal; P1.1 is connected to the byte identification signal HBIL, which controls whether the read-write data belongs to the 1st or 2nd byte of a 16-bit word; P1.2 and P1. 3 Connect HCNTL0 and HCNTL1 respectively to realize the access to HPIC, HPIA and HPID registers; nRD and nWR connect nHDSl and nHDS2 as data strobe signals to latch valid HCNTLO/1, HBIL and HR/W signals. nINT1 is used as an input, and is connected with the host interrupt signal nHINT of the HPI port. nHCS is always grounded, and the nHAS port is connected to the ALE port. After the HCNTL0/I, HBIL and HR/W signals are valid, set nHDSl to low level to realize the read and write data strobe, thus completing the C51 to VC5402 Read and write operations of the HPI port. In the process of data exchange, when C51 sends data to HPI, it interrupts VC5402 by setting the DSPINT bit in the HPI control register HPIC of VC5402 to 1. When C51 receives the data from HPI through the query mode, when the VC5402 DSP is ready to send data, the nHINT signal is set to be low; when the C51 inquires that nlNTl is low, it calls the receiving data subroutine to realize the data reception.

The parallel connection between C51 and VC5402 is shown in Figure 5.

The host receives and sends the initialization procedure (take the connection in Figure 5 as an example):

RTITEADDRESS: ;Write VC5402 memory address information
CLR P1.2
Note: ①HBlL pin indicates whether the current byte is the 1st or 2nd byte during the transmission process.
② In order to facilitate the DSP bootstrap loader. It is often used to connect the nHlNT pin directly with INT2
feet connected.
Figure 5 Parallel connection between AT89C51 and V05402
SETB P1.3; The host can read and write the HPlA address register
CLR P1.0; the host requests to write strobe HPI-8
MOV P0, A; write 8-bit address
CALL DELAY ; wait for the address write to complete
READDATA:; read out VC5402 memory data information
SETB P1.2
CLR P1.3; the host can read and write HPID data register
SET P1.0; the host requests to read the strobe HPI-8
MOVA, P0; read 8-bit data
CALL DELAY ;Wait for data readout to complete
WRITEDATA:; write VC5402 memory data information
SETB Pl. 2
CLR P1.3; the host can read and write HPID data register
CLR P1.0; the host requests to write strobe HPI-8
MOV P0, A; write 8-bit data
CALL DELAY ; wait for data writing to complete

Whether it is a serial connection or a parallel connection, it must be taken into account that VC5402 is powered by 3.3 V, and C51 is powered by 5 V. There is a difference in signal level between the two and cannot be directly connected, and the interface isolation device should be interconnected.

Epilogue

During the debugging of SCI serial communication, it was found that the internal data clock CLKG was too fast due to the operating frequency of DSP at about 100 MHz, which could not be consistent with the sampling frequency of the C51 serial port. It needs to be processed by software, which will consume additional DSP resources. Therefore, it can be considered to connect the sending clock CLKX and the receiving clock CLKR to an external clock source (slower than the DSP clock) to ensure the consistency with the sampling frequency of the C51 serial port. In addition, in the debugging of parallel communication, it can be known that there is no hardware and software overhead in parallel communication through the HPI-8 port, and the conflict is coordinated by the hardware of the DSP itself. Therefore, the HPI-8 port is used for the master-slave dual CPU that is better with the single-chip component. processor platform.