Design of a low-noise 12 GHz microwave fractional-N phase-locked loop

Circuit functions and advantages

This circuit is a complete implementation of low-noise “title=”low-noise”>low-noise microwave” title=”microwave”>microwave fractional-N PLL, with ADF4156 as the core fractional-N PLL device. Use the ADF5001 external prescaler to extend the PLL frequency range to 18 GHz. The microwave VCO is driven by an ultra-low noise OP184 operational amplifier with proper offset and filtering, and a completely low-noise PLL can be realized at 12 GHz. The measured integrated phase noise is 0.35 ps rms. This function is usually used to generate the local oscillator frequency (LO), which is suitable for applications such as microwave point-to-point systems, test and measurement equipment, automotive radars, and military applications.

Design of a low-noise 12 GHz microwave fractional-N phase-locked loop

Figure 1. Low-noise microwave fractional-N PLL (simplified diagram: decoupling and all connections not shown)

Circuit description

Figure 1 shows a block diagram of the circuit. The circuit chose the 12 GHz VCO DXO11751220-5 from Synergy Microwave. Of course, any VCO in the 4 GHz to 18 GHz range can be used as long as the loop filter is appropriately redesigned. Like most microwave VCOs, Synergy VCOs have a wide input tuning range of 0.5 V to 15 V, which requires an active PLL loop filter between the low-voltage ADF4156 charge pump (maximum output is 5.5 V) and the VCO input. OP184 was selected as the operational amplifier of the active loop filter due to its excellent noise performance and rail-to-rail input/output. The output noise of the operational amplifier will be fed through to the RF output and will be shaped by the active filter, so the noise is low. Rail-to-rail input operation is also an important consideration for PLL active filters because a single op amp power supply can be used. This is because the charge pump output (CPOUT) will start at 0 V at power-up, which may cause problems for op amps that do not have a rail-to-rail input voltage range. This also allows the non-inverting input of the op amp to be biased to a voltage higher than ground, and there is a built-in margin for any bias voltage changes caused by resistance mismatch or temperature changes. It is recommended to set the bias level to about half of the charge pump power supply (VP), which not only meets the input voltage range requirements but also leaves sufficient margin, and obtains the best charge pump spurious performance. This circuit note uses VP = 5 V for measurement, and the op amp common-mode bias voltage = 2.2 V. In order to minimize the reference noise feedthrough, a large 1μF decoupling capacitor is placed near the input pin of the non-inverting operational amplifier, as shown in Figure 1. This capacitor and 47 kΩ resistor form an RC filter with a cut-off frequency below 10 Hz.

Loop filter design

What this circuit chooses is the inverted topological structure of pre-filtering. It is recommended to use pre-filtering to avoid overdriving the amplifier with very short current pulses from the charge pump-this may limit the slew rate of the input voltage. When using an inverting topology, you must ensure that the PLL IC allows PFD polarity inversion to offset the inversion of the op amp and drive the VCO with the correct polarity. The ADF4156 PLL has this PD polarity option.

Setup and measurement

Table 1 shows the setting of the circuit. Figure 2 shows the comparison between the measurement results and the predicted simulation performance of ADIsimPLL. It can be seen that the results are very consistent. The measured integrated phase noise is 0.35 ps rms. The measurement setup is shown in Figure 3.

Table 1. Test measurement settings

Design of a low-noise 12 GHz microwave fractional-N phase-locked loop

The performance of this circuit or any high-speed circuit is highly dependent on proper PCB layout, including but not limited to power bypass, controlled impedance lines (if necessary), component layout, signal routing, and power and ground planes.

Design of a low-noise 12 GHz microwave fractional-N phase-locked loop

Figure 2. Comparison of measured performance and simulated phase noise performance of a 12 GHz PLL

Figure 3. Measurement circuit

Common changes

There are several active loop filter topologies in ADIsimPLL with inverting or non-inverting operational amplifier configurations. The choice of phase noise can be analyzed in ADIsimPLL. The reverse topology allows the output voltage to be as low as the minimum output voltage of the operational amplifier, which can be as low as 125 mV for the OP184. In contrast, the output voltage of a non-inverting topology is limited to the product of the minimum charge pump voltage (0.5 V) and the non-inverting gain.

The Links:   LM150X08-B3 PS11036-Y2


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