“Today’s analog-to-digital converter (ADC) uses the latest technology to collect analog signals with high precision and fast sampling frequency. The complexity of the data converter increases with the increase in sampling frequency and accuracy. The specification of high-performance data converters must follow strict input conditions to maximize the expected performance of the device. A very challenging input condition is to measure, drive and interface the ADC input analog signal. This article will discuss some techniques for efficient interface connections to high-speed ADCs to optimize ADC performance.

“

Today’s analog-to-digital converter (ADC) uses the latest technology to collect analog signals with high precision and fast sampling frequency. The complexity of the data converter increases with the increase in sampling frequency and accuracy. The specification of high-performance data converters must follow strict input conditions to maximize the expected performance of the device. A very challenging input condition is to measure, drive and interface the ADC input analog signal. This article will discuss some techniques for efficient interface connections to high-speed ADCs to optimize ADC performance.

In terms of effective input drive to maintain signal integrity, there have been many good application notes and articles published. This article will explore new developments related to input drives.

ADC input architecture and driver selection

The ADC’s analog input configuration varies with the sampling accuracy and maximum sampling frequency. In the input stage, the characteristics that affect the selection of the input driver are:

1. Single-ended and differential

2. High impedance and low impedance (100W) (or buffered or unbuffered)

Single-ended and differential

Most ADCs that push sampling accuracy and sampling frequency to the limit use differential input. The advantage of differential input is to reduce even harmonics and EMI. Some differential input ADCs have an IRS (input range selection) register, which allows users to use the device as a single-ended input by connecting unused inputs to a common mode (CM) A/D conversion reference.

Buffered and unbuffered

High-sampling frequency ADCs (>500 MSPS) often have to deal with high-frequency analog input signals. Assuming that the standard PCB board size and track length are used, if this high-frequency analog signal does not end normally and is processed in the same way as the radio frequency signal and the circuit board, the analog signal will degenerate. Such high frequency applications benefit from low impedance (50W single-ended or 100W differential) analog input. Therefore, most UHF and VHF circuits are 50W systems. In order to obtain higher distortion performance, differential input is usually used. Due to strict specification restrictions and high frequency effects, high sampling rate ADCs usually do not provide IRS options that allow the use of single-ended inputs. The reason is: ADCs using IRS require additional circuitry to convert to full scale (FSR), which is not feasible for applications at high frequencies/high sampling rates. Therefore, this level of ADC requires high-frequency, low-resistance (100W differential) input drive. With a low resistance input ADC, the analog input is buffered before being applied to the sample/hold (S/H) circuit for conversion. Therefore, it is not necessary to adopt the standard decoupling circuit used in unbuffered ADCs (series resistance R, parallel capacitance C). In the diagram in Figure 1, an unbuffered input ADC (ADC10080) is used. These decoupling components are identified as R1, R2 (18W) and C1 (25W) in the figure.

Conversion from single-ended to differential

Neutral point connection transformer

(Ruthroff transformer)

As mentioned earlier, the input driving the differential ADC must be in differential form. Converting a single-ended input to a differential signal usable by the ADC requires the use of a midpoint wiring transformer, as shown in Figure 1 (under the dashed line of “differential input” you can see how the transformer is connected to the ADC input).

The common-mode voltage (CM) of the differential input should follow the VCOM voltage (the output pin on the ADC) in order to make the sample-and-hold circuit inside the ADC work normally. The circuit in Figure 1 allows the input CM to be set by connecting the midpoint wiring of the transformer to the ADC’s VCOM output.

The lower cut-off frequency of the transformer does not allow low frequency content to be coupled in. Therefore, this form of coupling can only be applied to systems that do not require DC and low-frequency content. In addition, this circuit also bears the leakage effect of the high-frequency transformer, which limits its upper operating frequency. Typical transformers have upper and lower operating frequencies. The lower frequency limit is determined by the primary inductance. For this transformer used with the 8-bit converter, if other gain calibration or adjustment methods are not used, the working frequency band is very narrow, limited to 1 MHz ~ 100MHz, where the insertion loss change is less than 0.034dB (1 LSB).

For maximum return loss (minimum reflection), many higher speed applications require the input impedance at J1 (input connector) in Figure 1 to be controlled and matched to the characteristic impedance of the cable connected to the connector. This requirement is particularly important when the length of the cable exceeds 1/20 of the shortest wavelength encountered. As long as the transformer return loss does not degrade at the extreme frequency, it is possible to achieve this goal by setting a terminal resistor RT through the input. In this way, the input impedance will be close to RT, because the return loss of the transformer has increased enough to have a minimum load effect. At higher frequencies, the use of this type of transformer configuration will make it more difficult to control the input due to the reduction in transformer return loss. And this is where the advantage of the unbalanced transformer lies.

Unbalanced transformer

(Guanella transformer)

Another method for single-ended to differential conversion is to use a balun, as shown in Figure 2.

Compared with Figure 1, this method has the following advantages and disadvantages:

advantage:

1. Higher operating frequency

2. For broadband applications, there is a higher return loss

3. Better gain and phase balance

shortcoming:

1. Cannot set common mode voltage

2. Unable to provide voltage gain

Compared with the midpoint connection transformer or Ruthroff transformer in Figure 1, the unbalanced configuration has a higher operating frequency. However, after the unbalanced configuration is adopted, because the common mode voltage level cannot be set, the ADC input must be an AC coupling voltage. Take ADC08D1500 as an example. It is an 8-bit, 1500MSPS converter. If it works in AC-coupled mode, it will automatically bias its input to an appropriate common-mode voltage value through internal resistors. If the ADC’s VCMO output is grounded, it will operate in AC coupled mode.

As shown in Figure 2, using an AC coupling capacitor (4.7nF), the -3dB frequency of the input coupling circuit is approximately 677 KHz (=1/(2pReqCeq), where Req=100W, Ceq=4.7nF/2=2.35nF) . This 100W equivalent resistance is the series combination of the coupling capacitor (RT2 is connected in parallel with the ADC’s 100W input, 50W in total), the differential load on the right and the differential impedance between pin 1 and pin 3 (50W) of the balun.

Using the circuit in Figure 2, J1 is terminated at about 50W, and it is assumed that the ADC being driven has a differential input terminal of 100W (such as ADC08D1500). RT2 in parallel with 100W ADC input impedance is 50W, which is the input impedance from J1 to ground. This input impedance has been maintained at a certain frequency, so that the balun can play the role of a transformer. Beyond this frequency range based on the special balun and its core characteristics, inter-coil capacitance, and other factors, the input impedance will deviate from this value, and input reflection will reduce the return loss. Most product manuals of unbalanced transformers list the return loss and upper and lower operating frequencies of several frequency points.

Figure 3 shows the input return loss of a midpoint connection transformer (TC4-14) and a balun transformer (TC1-1-13M), and a simple comparison is made.

It can be seen from Figure 3 that when the return loss of the mid-point connection transformer is below 700MHz and above 1.3GHz, it drops very quickly, while the unbalanced transformer has a certain return loss that is several MHz higher (> 10dB) And it starts to drop when the frequency reaches about 2.6GHz. This is the advantage of the unbalanced transformer over the midpoint connection transformer. The reduced return loss at higher frequencies will cause a mismatch and produce higher reflected energy, which will form unwanted harmonics in the collected signal and reduce the ENOB performance of the system.

Return loss (RL) is related to the two-port input impedance, as shown in Equation 1:

RL= 20 Log | (Zin+50)/ (Zin-50) | (1)

For example, an RL of 10dB corresponds to an input impedance of 96W or 26W (depending on the sign of the quotient in Equation 1). The reflected wave when the impedance is discontinuous (J1 in Figure 2) will reach Rs1 after another reflection from the source end (assuming that the source and the transmission line are not perfectly matched). The round trip time is l/n, where l is the length of the cable and n is the wave speed through the transmission line medium. The different frequency components that make up the input signal will return to the interruption after encountering this round-trip delay and adding the original incident wave to form the final signal. For the round-trip delay (2l/n), l is an important harmonic (about 1/10 of the period T), and the final waveform will be distorted. Mathematically speaking, T here satisfies the harmonic requirement of T ≤ (20 l/n). The reason is that for shorter-period harmonics, the incident and reflected waves will synthesize (in time) overlapping forms, which will cause the waveform to change. This is the reason for the reduction in ENOB, because this changed waveform will increase the distortion term of total harmonic distortion (THD), resulting in a lower ENOB.

In order to balance the unbalanced function, the primary and secondary of the transformer always maintain a 1:1 ratio, so this configuration cannot provide any voltage gain.

Active single-ended to differential conversion

As mentioned earlier, transformers can be used as converters, but they have great disadvantages in broadband applications, and in these applications, they will not include DC and low frequencies in their operating frequency region. For this reason, semiconductor manufacturers have introduced active devices to perform this function to make up for the shortcomings of the transformer coupling structure.

The LMH6555 is specifically designed to drive the 100W differential input of the ADC as shown in Figure 4 as 0.8Vpp, and provides a fixed 50W input impedance to the terminal cable (not shown in Figure 4) to achieve the highest return loss. The single-ended to differential converter will extend the frequency range from DC to 1.2GHz (this is the -3dB bandwidth limit of LMH6555). By connecting the VCMO of the ADC to the VCM_REF input of the LMH6555, accurate output common-mode voltage control can be maintained. With this structure, the full signal spectrum can be obtained, and the common mode control can be automatically realized by LMH6555. The buffer (LMV321) shown in Figure 4 is used to increase the current flowing out of the ADC’s VCMO pin, so that it has an appropriate drive capability for the VCM_REF input. Whether or not a buffer is needed depends on the current output capability of the ADC. The gain of LMH6555 (differential output under Vin+ to single-ended or Vin+ depending on the driven input) is determined at 4.8V/V, and its configuration is shown in Figure 4, where Rs1=Rs2=50W. For the case where the input signal has a large amplitude, the LMH6555 insertion gain can be reduced by increasing the values ​​of Rs2 and Rs1. These two resistances should always be equal to maintain input balance for low output offset. In the example shown in Figure 5, the gain of the LMH6555 at the receiving end of the 50W cable is reduced by Rx and Ry. By selecting component values, the input impedance of the LMH6555 circuit (J1) is kept at 50W to match the impedance. Two LMH6555 have 100W equivalent impedance to ground, and each component value is displayed to maintain a low output offset voltage. The input/output swing relationship of LMH6555 is shown in formula 2:

Vout (Vpp) = Vin (Vpp) *[RF/ (2Rs+Rin_diff)](2)

Among them, RF=430W, Rin_diff=78W, both are specific values ​​of LMH6555.

Rs is the equivalent resistance, grounding the input of LMH6555 (assuming they are equal). Increasing Rs will reduce the gain. Rearrange Equation 2 to allow the user to determine the value of Rs and determine the input swing of the full ADC for a given Vin (Vpp), as shown in Equation 3:

Rs=Vin (Vpp) * 268.8 – 39 (3)

The equivalent input resistance of LMH6555 is increased to 100W through Rs (calculated by Equation 3), therefore, 0.52Vpp input will cause ADC input to be exactly 0.8Vpp, while the equivalent input of J1 is maintained at 50W.

LMH6555 will maintain low noise (refer to the flat band of 19nV/RtHz output) and has nothing to do with its input Rs. This is because the input architecture of the LMH6555 is determined by the equivalent input noise voltage and is independent of the source resistance.

The ADC requires that the common-mode voltage (within +/-50mV) of the differential input is very close to the VCMO reference output it generates. This is a result of using a 1.9V supply voltage, because the lost supply voltage reduces the voltage margin inside the ADC. If this common mode operation is not maintained, the full distortion performance of the ADC will quickly deteriorate.

In addition to this common-mode phenomenon, any gain and phase imbalance at the two inputs of the ADC will result in incorrect signals being obtained. For example, a 100MHz square wave will have a 1.5% error at its peak. The 8-bit data acquisition has an LSB of 0.39% of the full scale, and the balun is equivalent to 3.8 LSB. Therefore, it is necessary to minimize gain and phase imbalance.